1Field of the Invention
The present invention relates to a microprogram control circuit for a microprocessor which controls processings in accordance with micro instruction, and more particularly to means for a changing function of the micro instruction.
2. Description of the Prior Art
FIG. 11 is a block diagram showing a structure of a conventional microprogram control circuit. In FIG. 11, numeral 1 represents microinstruction memory means (hereinafter referred to as micro ROM) for storing microinstruction, numeral 2 represents micro data indicating the contents of the microinstruction read out from the micro ROM 1, numeral 3 represents a micro data register for holding the micro data, numeral 4 represents a micro decoder for decoding the micro data 2 and parameter information, numeral 5 represents a control signal decoded by the micro decoder 4, numeral 6 represents micro address for designating execution entry of the microinstruction, numeral 7 represents a micro pointer for accessing the micro ROM 1 in accordance with the micro address 6, numeral 8 represents a micro counter for counting up the micro address 6 of the micro pointer 7, numeral 9 represents micro next address for designating next micro address 6 in accordance with contents of an address field in the micro data 2, numeral 10 represents a micro next address register for storing the micro next address 9, numeral 11 represents a micro stack register for storing the micro address 6 of returning place in case of execution of a subroutine in accordance with the microinstruction, numeral 12 represents an instruction decoder for decoding an instruction fetched from outside, numeral 13 represents a decoder code decoded by the instruction decoder 12, numeral 14 represents a micro address register for holding micro address code which designates start entry address of the microinstruction in the decoder code 13, numeral 15 represents a micro parameter register for storing the parameter information of addressing mode and others in the decoder code 13, and numeral 16 represents micro parameter.
FIG. 12 is a diagram showing instruction format for illustrating selecting method of start entry of the microinstruction at each instruction in the conventional example. In FIG. 12, numeral 17 denotes 1-word instruction, numeral 18 denotes 2-word instruction, numeral 19 denotes op codes for defining instruction operation, numeral 20 denotes destination fields for designating address of destination data and access method, numeral 21 denotes size fields for designating the size of source data, numeral 22 denotes source fields for designating address of the source data and access method, and numeral 23 denotes an expansion field to be designated at the source field 22.
FIG. 13 is a diagram of an entry structure of a horizontal microinstruction. In FIG. 13, numeral 24 denotes a microinstruction, numeral 25 denotes a micro address field for designating the micro address 6 of next microinstruction, and numeral 26 denotes a micro sequence field for designating a processing sequence of the microprogram.
The operation of the conventional example will be explained referring to FIGS. 11, 12, and 13 hereinafter. A generating method of the decoder code 13 will be firstly explained. An instruction fetched from an external memory device (not shown) is sent to the instruction decoder 12. At the instruction decoder 12, the type of the instruction is specified by the op code 19, so that the micro address code corresponding to the start entry of the microinstruction 24 is generated. At the same time as the generation of the micro address code, parameter information code is generated in accordance with the addressing mode and register number for accessing the source data and the destination data to be designated at the destination field 20 and the source field 22 and with the size information of the source data to be designated by the size field 21. The micro address code and the parameter information code are outputted from the instruction decoder 12 as the decoder code 13. The micro address code is stored in the micro address register 14 and the parameter information code is stored in the micro parameter register 15.
When there is additional information such as offset information and immediate data for an addressing mode to access the source data by the 2-word instruction 18, differing from the 1-word instruction 17, those information is given as the expansion field 23 designated at the source field 22. The size of the expansion field 23 (1 word) and whether the expansion field 23 exists or not are also given to the decoder code 13 together with the addressing mode and register number as a parameter information code of the source field 22. Therefore, the start entry of the microinstruction 24 to be designated at the op code 19 is not fixed by instruction format. That is, the start entry address of the microinstruction 24 is decided only by the op code 19 irrespective of the contents of the source field 22 and the destination field 20. If the op code 19 shows the same processing contents, the micro address 6 will be identical even in a case of 1-word instruction 17 without the expansion field 23 and 2-word instruction 18 with the expansion field 23.
The read out operation of the microinstruction 24 will be next explained. When the decoder code 13 is inputted in the micro address register 14 and the micro parameter register 15, the read out operation of the micro ROM 1 will be started. Firstly, the micro address 6 is read out from the micro address register 14 and the micro parameter 16 is read out from the micro parameter register 15. The micro address 6 is held in the micro pointer 7 and the micro parameter information 16 is held in the micro decoder 4. The micro pointer 7 accesses the microinstruction of the micro ROM 1 in accordance with the micro address 6 and reads out the microinstruction 24 to the micro data register 3 as a micro data 2.
The operation differs as follows dependent on the obtaining method of the micro address 6 to be executed next to be designated at the micro sequence field 26 of the microinstruction 24.
Firstly, when the microinstruction does not branch, the micro data 2 is outputted to the micro decoder 4 from the micro data register 3. The micro decoder 4 decodes the micro parameter 16 held previously and the micro data 2 so as to generate the control signal 5 for controlling operation device and others. At the same time that the micro data 2 is outputted to the micro decoder 4 from the micro data register 3, next decoder code 13 is set in the micro address register 14 and the micro parameter register 15. When the micro sequence field 26 of the microinstruction 24 indicates a termination of the microinstruction 24, the micro address 6 for processing next instruction is outputted to the micro pointer 7 from the micro address register 14 and the micro parameter 16 is outputted to the micro decoder 4 from the micro parameter register 15, and new microinstruction 24 is read out from the micro ROM 1.
When an instruction decoded at the instruction decoder 12 is to be processed by a plurality of microinstructions 24, the micro address 6 of the micro pointer 7 is counted up by the micro counter 8 until the micro sequence field 26 indicates a completion of the microinstruction 24 concurrently with the reading out of the microinstruction 24 from the micro ROM 1. The The micro address 6 counted up reads out next microinstruction 24.
Further, when the micro sequence field 26 of the microinstruction 24 indicates branching of the microinstruction 24 and the microinstruction 24 branches, that is, when the instruction decoded at the instruction decoder 12 is to be processed by a plurality of microinstructions 24, the micro data register 3 slices off the micro address field 25 of the micro data 2 as a micro next address 9 so as to outputs it to the micro next address register 10. On the other hand, the micro data 2 being sliced off for the micro address field 25 is outputted to the micro decoder 4 from the micro data register 3. The micro decoder 4 generates the control signal 5 in the same way as the above. At this time, the micro pointer 7 reads the micro address 6 from the micro next address register 10 until the micro sequence field 26 indicates non-branching of the microinstruction 24 or termination, and reads out next microinstruction 24.
Lastly, when the micro sequence field 26 of the microinstruction 24 indicates subroutine branching of the microinstruction 24 and the microinstruction 24 performs micro subroutine, that is, when an instruction decoded at the instruction decoder 12 is to be processed by the microinstruction 24 which is common to other instruction, the micro output register 3 slices off the micro address field 25 of the micro data 2 as a micro next address 9 in subroutine jumping place, and transmits to the micro next address register 10. On the other hand, the micro data 2 of which the micro address field 25 is sliced off is transmitted to the micro decoder 4 from the micro data register 3. The micro decoder 4 generates the control signal 5 in the same way as the above. At this time, the micro address 6 of the micro pointer 7 is counted up at the micro counter 8 concurrently and is stored in the micro stack register 11 as a returning address of the micro subroutine. The micro address 6 in the micro subroutine branching place is read in the micro pointer 7 from the micro next address register 10, so as to perform the process which is under subroutine branching. When the micro sequence field 26 indicates the completion of the micro subroutine branching, the micro pointer 7 reads in the micro address 6 of the micro stack register 11 as a returning address of the subroutine, and next microinstruction 24 is read out.
The timing of the above-mentioned operation will be briefly explained referring to FIGS. 14, 15, 16, and 17. In the Figures, numeral 27 indicates processing flow of an instruction I, numeral 28 indicates processing flow of an instruction II, and characters A, B, C, and D indicate operation cycle for reading out the microinstructions. Arrows indicates moving direction of data. Here, the same reference numbers or characters as FIG. 11 denote like functions.
Basically, 4 cycles of A, B, C, and D represent a read out cycle of one microinstruction.
Referring to FIG. 14, a case where a process of an instruction decoded at the instruction decoder 12 terminates with one microinstruction will be firstly explained. At the cycle D (the word "cycle" will be omitted hereinafter) prior by one to the start of reading out from the micro ROM 1, the decoder code 13 of the instruction I is outputted from the instruction decoder 12 and the micro address 6 is inputted to the micro address register 14. The micro address 6 is read in to the micro pointer 7 at A, the micro ROM 1 is accessed at B, the micro data 2 is read in the micro data register 3 at C and decoded by the micro decoder 4 together with the micro parameter 16 at D, and the control signal 5 is outputted at next A.
At this time, the decoder code 13 of the instruction II is outputted from the instruction decoder 12 at D and is processed in the same way as the instruction I.
Next, a method for obtaining the micro next address in case of a process to be performed by a plurality of microinstructions will be explained. A case where the microinstruction does not branch will be explained referring to FIG. 15. The micro address 6 of the micro pointer 7 is fetched by the micro counter 8 and counted up at C and delivered to the micro pointer 7 at D. Next microinstruction is accessed by the micro pointer 7 at next B.
When the microinstruction branches in the same condition, as shown in FIG. 16, the micro next address 9 which is indicated by the address field 25 of the microinstruction sliced off by the micro data register 4 at C is stored in the micro next address register 10. Then, it is delivered to the micro pointer 7 at next A and the microinstruction in branching place is accessed by the micro pointer 7 at next B.
When the subroutine branches in the same condition, as shown in FIG. 17, the micro address 6 of the micro pointer 7 is fetched by the micro counter 8 at C and counted up, and is delivered to the micro stack register 11 at D. Then, it is delivered to the micro pointer 7 at next A and the microinstruction in the branching place is accessed by the micro pointer 7 at next B.
In the conventional microprogram control circuit, the execution procedure of the microinstruction can be changed by changing the programming of the micro address field and micro sequence field in the microinstructions. It is easily implemented by changing the data for programming in the micro ROM in the process of manufacturing.
However, when new addition of the instruction and expansion or change of the function of the instruction are required, programming is necessary in the added expansion micro ROM on new chips. Consequently, the circuit should be changed widely in order that the instruction decoder can decode the micro address of the micro ROM which is newly expanded.
Accordingly, there are problems in the conventional microprogram control circuit that it takes long time to develop a product provided with new function and manufacturing cost will be increased.